$1)$ Architectures are considering one of two changes to their processor. The first is to increase the clock speed from $3$GHz to $4\mathrm{.}5$GHz$.$ The estimate is that the $4\mathrm{.}5$GHz processor will stall $25\%$ of the time. The second is to add a branch prediction buffer $($cache$)$ which, when accurate, removes branch penalties. A branch without penalties is $1$ cycle whereas with a penalty is $3$ cycles. The prediction buffer is thought to be $60\%$ accurate. What are the speedups of both enhancements?