1. Assume the following MIPS code is executed on the above pipelined processor:

.data x: .word 4, 12, 10, 21, 7 .text

add $t0, $0, $0 addi $t1, $0, 20 loop: beq $t0, $t1, done lw $s0, x($t0) addi $t0, $t0, 4 j loop done: addi $s0, $s0, 5 sw $s0, x($t0)

a. Draw the pipeline execution diagram for this code, assuming no delay slots and that branches executes in the EX stage. b. Repeat (a), but assume that delay slots are used