$($b$)$ Control Path $-$ For the given code, write the values of the control signals for each instruction.

You may group the instructions with the same control signals.

The control signals to be included are: ALUOp, ALU control output $($ALU ctrl$),$ Branch, Jump, PCSrc$,$ Regdst, ALUSrc, MemtoReg, RegWrite, MemRead and MemWrite

$\backslash$table$[[$Instr$,\backslash$table$[[$ALU$],[$Op$]],\backslash$table$[[$ALU$],[$ctrl$]],\backslash$table$[[$Reg$],[$dst$]],\backslash$table$[[$ALU$],[$Src$]],\backslash$table$[[$Memto$],[$Reg$]],$Branch,Jump,$\backslash$table$[[$PC$],[$Src$]],\backslash$table$[[$Reg$],[$Write$]],\backslash$table$[[$Mem$],[$Read$]],\backslash$table$[[$Mem$],[$Write$]]],[,,,,,,,,,,,]]$

$($c$)$ Execution Time $-$ For the given code, compute the execution time for each instruction and for the complete code based on the following information.

$($i$)$ Given the following access times for the critical functional units, compute the time taken to execute each instruction. You may group the instructions with the same execution time.

Memory Access $=0\mathrm{.}25ns$;

Register Access $=0\mathrm{.}13ns$;

ALU execution $=0\mathrm{.}18ns$

$($ii$)$ Assuming all instructions are executed using a fixed clock cycle length. What is the execution time for the complete code$/$program$?$Question $1$: The following MIPS Code is executed using the single cycle MIPS architecture. Include all iterations of the loop while answering the questions.

Start: addiu $t$6,$ $$0,64$

addi $t$8,$ $$0,8$

add $s$1,$ $s$0,$ $t$8$

Loop: slt $t$0,$ $s$0,$ $s$1$

beq $ to$,$ $$0,$ Exit

lbu $t$1,0($$$s0)$

sub $t$1,$ $t$1,$ $t$6$

sb $t$1,0($$$s0)$

addi $s$0,$ $s$0,1$

j Loop

Exit:

$($a$)$ Data Path $-$ For the given code, write the Functional Units used in order.

Specify if any Functional Units $($FUs$)$ are used at the same time for the same instruction, for example $PC+4$ Adder is used while Instruction Memory is in use.

For Multiplexors, if the output of the MUX is used, then it implies that the MUX is used $($i$.$e$.,$ if the select lines are $0$ or $1$ and not don't cares, then the MUX is used$).$ Similarly, if any $FU$ output is unused, we assume that the FU is unused.

You may group the instructions with the same datapath.

You may use the following notations for the Functional Units or the image on the next page.

Instruction Memory $($IM$),$ Data Memory $($DM$),$ Register File $($RF$),$ Arithmetic and Logical Unit $($ALU$),$ Program Counter Register $($PC$),$ Sign Extension block $($SE$),$ Control Unit $($ctrl$1),$ ALU control unit $($ctrl$2),$ PC$+4$ Adder $($add$1),$ Branch PC target Adder $($add$2),$ Shift Left $2($sII$),$ Regdst MUX $($mux$1),$ ALUSrc MUX $($mux$2),$ MemtoReg MUX $($mux$3),$ PCSrc MUX $($mux$4),$ Jump MUX $($mux$5).$

Question $1$: The following MIPS Code is executed using the single cycle MIPS architecture. Include all iterations of the loop while answering the questions.$($a$)$ Data Path $-$ For the given code, write the Functional Units used in order.

Specify if any Functional Units $($FUs$)$ are used at the same time for the same instruction, for example PC$+4$ Adder is used while Instruction Memory is in use.

For Multiplexors, if the output of the MUX is used, then it implies that the MUX is used $($i$.$e$.,$ if the select lines are $0$ or $1$ and not don't cares, then the MUX is used$).$ Similarly, if any $FU$ output is unused, we assume that the $FU$ is unused.

You may group the instructions with the same datapath.

You may use the following notations for the Functional Units or the image on the next page.

Instruction Memory $($IM$),$ Data Memory $($DM$),$ Register File $($RF$),$ Arithmetic and Logical Unit $($ALU$),$ Program Counter Register $($PC$),$ Sign Extension block $($SE$),$ Control Unit $($ctrl$1),$ ALU control unit $($ctrl$2),$ PC$+4$ Adder $($add$1),$ Branch PC target Adder $($add$2),$ Shift Left $2($sII$),$ Regdst MUX $($mux$1),$ ALUSrc MUX $($mux$2),$ MemtoReg MUX $($mux$3),$ PCSrc MUX $($mux$4),$ Jump MUX $($mux$5).$