$1$ Background

In the previous activity we learned how to use a single cache level to profile requests to the memory. Today we

will learn two new concepts: cache levels and set$-$associative caches. The processor has many cache levels that are

progressively larger in size. If a row hits capacity and a block is lost, there is a chance it will still be contained in a

lower level of the cache. The general for for any cache level $i$ is this:

The input to the cache level is a request for an aligned memory address. ${?}^1$

Go to the appropriate row, check the valid bit, and check if the tag matches.

$($a$)$ If the valid bit is zero, it is a miss cold start. Push the request to a lower level.

$($b$)$ If the tag is mismatched, it is a miss. If there are no free blocks it is a capacity miss. Push the request to

a lower level

$($c$)$ If the tag matches, it is a hit. Return the block in this row up to a higher level.

The levels of a cache are generally:

Level $1($L$1).$ In practice, there are two level $1$ caches, one for instructions and one for data. For our assignments

we will have a single L$1$ to keep things simple.

L$2$

L$3.$ In practice, this level is shared across multiple logical processors, but this will not come into play for our

assignments because we only work with a single logical processor.

The virtual memory.

The processor starts on level $1$ and works its way down.

n$-$way Set Associative Cache With the last question on the last activity, we experienced a major flaw in our

direct$-$mapped cache design. You worked out an example where the cache kept juggling the block in and out of row

Each time it is a miss, this means it had to go to a lower level. The simplest way to address this is to have each

row hold multiple blocks. For example, with a direct$-$mapped cache, if you think about it in terms of a tuple:

Row, Tag, $v,$ Data