Question: 1 . Cache Performance [ 1 5 points ] Our embedded system has an 8 KB direct - mapped data cache with 8 - byte

1. Cache Performance [15 points]
Our embedded system has an 8KB direct-mapped data cache with 8-byte blocks. The cache is using write-back and write allocate policy. The cache is initially empty before executing the following code.
For (i=0;i<3;i++)
For (j=0;j<100;j++)
A[i][j]= B[j][0]+B[j+1][0];
The array A and B contain 4-byte elements. The array A has 3 rows and 100 columns. The array B has 101 rows and 3 columns. The layout for the array A is as follows. The array B has a similar layout.
Memory layout for array A.
A[0][0] A[0][1] A[0][2] A[0][3] A[0][4]
...
(a)[5 points] How many times does the array A cause cache misses when we running above code?
(b)[5 points] How many times does the array B cause cache misses when we executing above code? What type of locality do the accesses for the array B has?
(c)[5 points] Whats the total miss rate when we execute above code assuming cache is sufficiently big to contain array A and B?

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