1. Consider an L1 cache that has 8 sets, is direct-mapped (1-way), and supports a block size of 16 bytes. For the following memory access pattern (shown as byte addresses, assume 8-bit width), show their offset, index, and tag value.

For each hit, indicate the set that yields the hit, for each miss, indicate if it is compulsory miss (cp) or conflict miss (cf). Assume the following addresses are 8-bits wide. 0, 8, 4, 16, 130, 24, 36, 42, 48, 8, 4, 147.

byte number	offset	index	tag	hit/miss and reason
0
8
4
16
130
24
36
42
48
8
4
147