1. Consider the following assembly code. 1. LOAD R, #1 2. LOAD S #31 3. LOAD T, #(k-3) 4. ADD AC, R, S 5. LOAD R, S 6. LOAD S, AC 7. T- 8. BRP 4, T 9. STOR AC, M. where R, S, T, AC are registers, M is a memory location, # indicates immediate addressing and BRP stands for "branch if positive". (b) Explain the effect of the branch instruction on performance when the code is executed on a pipelined processor. (6 marks) (8 marks) (c) Explain how a RISC machine would minimize the number of delay slots.