1. Consider the MIPS pipeline discussed in class, suppose the register between the Instruction Decode and Execute stages were removed. a. How would this affect the clock cycle? b. What is the speedup of the five stage pipeline vs. this new four stage pipeline? Assume ideal CPI for both cases. c. If the CPl of the five stage pipeline was not ideal, calculate by how much the NOPs would have to be reduced to make the change in the design (from five to four stages) beneficial in terms of performance