$1.$ Consider a simple MIPS$-$like pipeline with the following stages:

$$ IF: Instruction Fetch

$$ ID: Instruction Decode

$$ EX: Execute

$$ MEM: Memory Access

$$ WB: Write Back

Assume the following two instructions execute sequentially:

I$1$: ADD R$1,$ R$2,$ R$3$ Adds the contents of registers R$2$ and R$3$ and stores the result in register R$1.$

I$2$: BEQ R$1,$ R$4,$ LABEL $$ Branches to the label LABEL if the values in registers R$1$ and R$4$ are equal.

A$)$ Explain how the BEQ instruction depends on the result of the ADD instruction.

$$

B$)$ Identify which pipeline stages are involved in forwarding$/$bypassing in this case.

$$

C$)$ Describe how forwarding can avoid pipeline stalls for this sequence of instructions.

$$

D$)$ Illustrate the pipeline stages over each clock cycle, indicating where the forwarded data is used to make the branch decision without delay. $5.$ Consider a simple MIPS$-$like pipeline with the following stages:

$-$ IF: Instruction Fetch

$-$ ID: Instruction Decode

$-$ EX: Execute

$-$ MEM: Memory Access

$-$ WB: Write Back

Assume the following two instructions execute sequentially:

I$1$: ADD R$1,$ R$2,$ R$3-$ Adds the contents of registers R$2$ and R$3$ and stores the result in register R$1.$

I$2$: BEQ R$1,$ R$4,$ LABEL $-$ Branches to the label LABEL if the values in registers R$1$ and R$4$ are equal.

A$)$ Explain how the BEQ instruction depends on the result of the ADD instruction.

B$)$ Identify which pipeline stages are involved in forwarding$/$bypassing in this case.

C$)$ Describe how forwarding can avoid pipeline stalls for this sequence of instructions.

D$)$ Illustrate the pipeline stages over each clock cycle, indicating where the forwarded data is used to make the branch decision without delay.