1) Consider the single-bit Full Adder constructed using 5 Boolean gates .We wish to use this Full Adder to construct a Ripple Carry Adder (RCA) for an add instruction in a CPU with a 32-bit wide ALU 1.1) Draw the circuit of the single 1-bit Full adder(3 level 2-inputs XORs and ANDs)? (do not draw the 32-bit RCA) 1.2) How many Boolean gates are required for this RCA? a) 5 gates (2 XOR, 2 AND, 1 OR) b) 10 gates (4 XOR, 4 AND, 2 OR) c) 50 gates (20 XOR, 20 AND, 10 OR) d) 160 gates (64 XOR, 64 AND, 32 OR) e) 320 gates (128 XOR, 128 AND, 64 OR) 1.2) If the propagation delay of each Boolean gate is 50 psec, then in the worst case how long would addition of two 32- bit numbers take using this RCA? a) 50 psec b) 1600 psec c) 4.8 nsec d) 480 nsec e) 1600 nsec 1.3) Given the above, suppose the clock period of this CPU is 1.2 nsec. What would the CPI for add be? Here assume any operations associated with an add instruction besides the RCA itself require negligible time (zero time for fetching instructions and operands from memory, zero time to access registers, zero time for control signals, etc.) a) 1.0 b) 1.7 c) 2.0 d) 3.0 e) 4.0