Question: 1. Design an 8-bit ADD/SUBTRACT unit using VHDL as follows: a) Use structural model with one-bit full adder as a basic component. b) Use a

1. Design an 8-bit ADD/SUBTRACT unit using VHDL as follows: a) Use structural model with one-bit full adder as a basic component. b) Use a data flow model. c) Use Behavior model. d) Use a mixed model. You are required to compare your design using the different models with respect to speed, size and efficiency

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