1) Determine the logic level for each input combinations in Table 1 so that the desired result can be realized. Each steps are in sequence. Table 1 Desired Result PRE CLR J K CLK Q 1 0 X X U Set initial value Q = 1 Output stays the same, no change to asynchronous input RESET Output Q is not the previous Q. no change to asynchronous input Output Q change to 0 SET 2) You are given a counter circuit as shown in Figure 1. Produce the next state diagram. Cnt D CK FF1 lol Clock a D >CK FFO lo Figure 1: A Synchronous Counter Circuit