1. Explain the concept behind pipelining using your own word 2. What are the pipeline hazard types that cause a slowdown in the pipeline? 3. Ignoring pipeline hazards and suppose each instruction takes 1 clock cycle to execute. In a five staged pipelined processor, we have: 1. Instruction Fetching (IF) stage takes 5 nanoseconds; 2. Instruction Decoding (ID) stage takes 3 nanoseconds; 3. Instruction Executing (EX) stage takes 3 nanoseconds; 4. Memory Operand Reading (MEM) stage takes 4 nanoseconds 5. Writing A Value back to register (WB) stage takes 4 nanoseconds. Also, the overhead from the added pipeline latches (pipeline registers) is 1 nanosecond. Questions: For the pipelined computer: The clock cycle time is determined by the worst case (the longest) stage plus the overhead from the added latches, which is going to be The clock rate is a reciprocal of the cycle time and it is going to be 1. 2. For the nonpipelined computer: Now for comparison purpose, let us remove the pipeline logic and pipeline latches from the processor so this processor has to execute each instruction sequentially one by one The clock cycle time becomes the total time it takes to execute an instruction, which is going to be The clock rate is a reciprocal of the cycle time and it is going to be 3. 4. Finally, the speedup ratio from the pipelining is 4. In theory, a k-staged pipeline computer may achieve a speedup of