1. Given the circuit in Figure 1, each two-input XOR gate has a propagation delay of 60 ps and a contamination delay of 40 ps.

Each flip-flop has a setup time of 60 ps, a hold time of 20 ps, a clock-to-Q propagation delay of 70 ps, and a clock-to-Q contamination delay of 50 ps.

(a) If there is no clock skew, what is the maximum operating frequency of the circuit?

?(b) How much clock skew can the circuit tolerate before it might experience a hold time violation?

Please give explanation to help understand, thanks!