1. Memory hierarchy:

Let us assume a 2-way set associative 128 KB L1 cache with LRU replacement policy. The cache implements write back and no write allocate policy. Cache block size is 16 Byte. Page size is 64 KB. The system has a direct mapped TLB with16 entries. TLB also implements LRU policy. Virtual address is 24 bit and physical address is 20 bit long. The cache is virtually indexed and physically tagged.

Please fill up the following the table. All numbers are in hexadecimal

Binary Addr Physical TLB TLB TLB Tag Index Hit R/W Addr Addr 16103A W 000101100001000000111010 17113CR 000101110001000100111100 26112BR 00100110000100010010 1011 16103B FR 00010 11000010000001110111 16103C W 000101100001000000111100 23113D R 00100011000100010011 1101 26103A R 00100110000010000001 11010 T171 13D FR 0001011 10001000 100111101 Table 1: Memory access sequence Virtual Page Physical Page 17 Table 2: Partial Page Table Cache Cache Index Ta TLB Index TLB Tag Physical Page V Table 3: TLB Found Way