$1.$ MIPS MUX Components Design

module mux$2$ #$($parameter WIDTH $=32)//$ WIDTH $=5$ for R$.$ F$.($d$0,$ d$1,$ s$,$ y$)$;

input $[$WIDTH$-1$:$0]$ d$0,$ d$1$;

input s;

output $[$WIDTH$-1$:$0]$ y;

endmodule

$2.$ MIPS IM $($Instr$.$ Mem.$)$ Component Design

module im$\_4$k$($ addr, dout $)$;

input $[11$:$2]$ addr;

output $[31$:$0]$ dout;

$...$

$...$

endmodule

$($PLEASE ADD CLK SIGNAL TO THIS MODULE$)$

$3.$ MIPS DM $($Data Mem.$)$ Component Design

module dm$\_4$k$($ addr, din, DMWr$,$ clk$,$ dout $)$;

input $[11$:$2]$ addr;

input $[31$:$0]$ din;

input DMWr;

input clk;

output $[31$:$0]$ dout;

$...$

$...$

endmodule

QUESTIONS.

$1.$ Basic specification of four components.

$2.$ Explanation of design with block diagrams.

$3.$ Test bench design.

$4.$ Test results: input data & waveform.

$($NOTE: USE THE ABOVE DIAGRAM AND THE CODES TO ANWANSWERER THIS QUESTIONS AND ALSO INCLUDES SCREENSHOTS OF THE TEST BENCH WHEN RUNNED$)*$ALSO ADD THE CLK SIGNAL TO CODE NUMBER $2,$ AS MENTIONED ABOVE$*$