$1.$ MIPS PC Component Design

module PC$($ cl

input rst; $//$reset pc to $32\text{'}$h$0000\_3000$

input PCWr;

input $[31$:$2]$ NPC;

output $[31$:$2]$ PC;

$...$

$...$

endmodule

$2.$ MIPS NPC Component Design

module NPC$($ PC$,$ NPCOp, IMM, NPC $)$;

input $[31$:$2]$ PC;

input $[1$:$0]$ NPCOp; $//$ PLUS$4(2\text{'}$b$00),$ BRANCH$(2\text{'}$b$01),$ JUMP$(2\text{'}$b$10)$

input $[25$:$0]$ IMM;

output $[31$:$2]$ NPC;

$...$

$...$

endmodule

$3.$ MIPS Extender Component Design

module EXT$($ Imm$16,$ EXTOp, Imm$32)$;

input $[15$:$0]$ Imm$16$;

input $[1$:$0]$ EXTOp; $//$ EXT$\_$ZERO$(2$b$00),$ EXT$\_$SIGNED$(2$b$01),$ EXT$\_$HIGHPOS$(2$b$10)$

output $[31$:$0]$ Imm$32$;

$...$

$...$

endmodule

$4.$MIPS ALU Component Design

module alu $($A$,$ B$,$ ALUOp, C$,$ Zero$)$;

input $[31$:$0]$ A$,$ B;

input $[1$:$0]$ ALUOp; $//$ ALUOp$\_$ADDU$(2\text{'}$b$00),$ ALUOp$\_$SUBU$(2\text{'}$b$01),$ ALUOp$\_$OR $(2\text{'}$b$10)$

output $[31$:$0]$ C;

output Zero;

$...$Single$-$Cycle Processor Datapath

$...$

endmodule

SEE THE ABOVE MODELS AND THE PICTURE AND GIVE RESULTS FOR THE FOLLOWING

Q$.$A$)$ Basic specification of four components.

Q$.$B$)$ Explanation of design with block diagrams.

Q$.$ C$)$ Provide Test bench design of this.

Q$.$ D$)$ Provide Test results: input data & waveform.