$1-$ Modify the single$-$cycle MIPS processor to implement one of the following in$-$

structions. See Appendix B for a definition of the instructions. Mark up a copy of

Figure $7\mathrm{.}11$ to indicate the changes to the datapath. Name any new control sig$-$

nals. Mark up a copy of Table $7\mathrm{.}8$ to show the changes to the main decoder. De$-$

scribe any other changes that are required.

$($a$)$ sll $($b$)$ lui $($c$)$ slti $($d$)$ blez $($e$)$ jal $($f$)$ lh

Table $7\mathrm{.}8$ Main decoder truth table to mark up with changes$2-$ The pipelined MIPS processor is running the following program. Which reg$-$

isters are being written, and which are being read on the fifth cycle?

add $$s0,$ $$t0,$ $$t1$

sub $$s1,$ $$t2,$ $$t3$

and $$s2,$ $$s0,$ $$s1$

$or$ $$s3,$ $$t4,$ $$t5$

$s1t$ $$s4,$ $$s2,$ $$s3$