Many processor architectures have a load with post-increment instIt is not possible to implement this instruction without either modifying the register file (adding another write port) or making the instruction take two cycles to execute. We modify the register file and datapath as shown in Figure 7.9. ruction, which updates the index register to point to the next memory word after completing the load. lwinc $rt, imm($rs) is equivalent to the following two instructions:

Repeat Exercise 7.3 for the lwinc instruction. Is it possible to add the instruction without modifying the register file?

Data from problem 3

Modify the single-cycle MIPS processor to implement one of the following instructions. See Appendix B for a definition of the instructions. Mark up a copy of Figure 7.11 to indicate the changes to the datapath. Name any new control signals. Mark up a copy of Table 7.8 to show the changes to the main decoder. Describe any other changes that are required.?

(a) sll?(b) lui(c) slti?(d) blez?

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1w $rt, imm($rs) addi $rs, $rs, 4