1. Please design a mod-16 asynchronous down counter by one J-K flip-flop with negative edge trigger (Fig. 1(@)), one S-R flip-flop with positive edge trigger (Fig. 1(b)), one D flip-flop with negative edge trigger (Fig. 1), and one T flip-flop with positive edge trigger (Fig. 1(d)). Note: you cannot use any basic logic gates to design this circuit. (16%) T J Q 5 Q D K ab- R ap- (6) ap- (d) (a) (c)