$1.$ Recall that we have two write policies and two write allocation policies, and their combinations can be implemented either in L$1$ or L$2$ cache. Assume the following choices for L$1$ and L$2$ caches:

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$1\mathrm{.}1$ Buffers are employed between different levels of memory hierarchy to reduce access latency. For this given configuration, list the possible buffers needed between L$1$ and L$2$ caches, as well as L$2$ cache and memory.

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$1\mathrm{.}2$ Describe the procedure of handling an L$1$ write$-$miss, considering the components involved and the possibility of replacing a dirty block.

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$1\mathrm{.}3$ For a multilevel exclusive cache configuration $($a block can only reside in one of the L$1$ and L$2$ caches$),$ describe the procedures of handling an L$1$ write$-$miss and an L$1$ readmiss, considering the components involved and the possibility of replacing a dirty block.