1. Unroll the given loop two times - your code should perform the equivalent of two loop iterations. Schedule it to minimize the number of both stall cycles and instructions executed; note which loop (A, B, or any combination thereof) each instruction corresponds to. You may assume the loop will be executed an even number of times and that there are sufficient operational units for all instructions. Registers F2, F4, and F6 are constants set prior to the loop. Register R1 is a variable set prior to the loop. Use the table below for latencies. Don't forget to indicate the locations of the stalls. (6 points) Code: FP Latencies: LOOP: L.D F5, O (R1) Producer of result Consumer of result Latency ADD.D F8, F5, F2 FP ALU op FP ALU OP 3 DIV.D 57, F4, F5 FP ALU op Store double 2 F3, F8, F6 Load double FP ALU OP 1 ADD.D FO, F7, F3 Load double Store double FO, 16 (R1) DADDUI RI, #32 BNE R1,RO, LOOP Branch delay slots: 1 MUL.D S.D 1. Unroll the given loop two times - your code should perform the equivalent of two loop iterations. Schedule it to minimize the number of both stall cycles and instructions executed; note which loop (A, B, or any combination thereof) each instruction corresponds to. You may assume the loop will be executed an even number of times and that there are sufficient operational units for all instructions. Registers F2, F4, and F6 are constants set prior to the loop. Register R1 is a variable set prior to the loop. Use the table below for latencies. Don't forget to indicate the locations of the stalls. (6 points) Code: FP Latencies: LOOP: L.D F5, O (R1) Producer of result Consumer of result Latency ADD.D F8, F5, F2 FP ALU op FP ALU OP 3 DIV.D 57, F4, F5 FP ALU op Store double 2 F3, F8, F6 Load double FP ALU OP 1 ADD.D FO, F7, F3 Load double Store double FO, 16 (R1) DADDUI RI, #32 BNE R1,RO, LOOP Branch delay slots: 1 MUL.D S.D