1. Write a Tcl script designed to analyze a given Verilog file and ascertain the count of occurrences for specific Verilog keywords: a. always b. initial c. end d. begin e. case f. module If a line is a comment (starts with // ), then you should not count these keywords contained in this line. Example following lines should not be counted: // always do your homework // initialize your design // ending..... Do not use any system calls (such as grep etc.) in this code.