Write a Shell script designed to analyze a given Verilog file and ascertain the count of

occurrences for specific Verilog keywords:

a$.$ always

b$.$ initial

c$.$ end

d$.$ begin

e$.$ case

f$.$ module

If a line is a comment $($starts with $//),$ then you should not count these keywords contained in

this line. Example following lines should not be counted:

$//$ always do your homework

$//$ initialize your design

$//$ ending $.....$

Use the shell commands only in the code. Do not use any other program $($such as TCL script$)$

inside your code. Please do it in basic and executable manner