1. Write behavioral VHDL code that implements the state machine that you designed in the previous module. Use a case statement to represent the state table as illustrated in the figure below. Use two processes one for the combinational logic and one for the state register. Add an asynchronous reset input. 1 entity SM17_2 is 2 port(X,CLK: in bit; 3 Z:out bit); 4 end SM17_2; 5 architecture Table of SM17_2 is 6 signal State, Nextstate: integer range 0 to 6:= 0; 7 begin 8 process(State,X) --Combinational Cicuit 9 begin 10 case State is 11 when 0=> 12 if X='0' then Z<='1'; Nextstate<=1; 13 else Z<='0'; Nextstate<=2; end if; 14 when 1=> 15 if X='0' then Z<='1'; Nextstate<=3 16 else Z<='0'; Nextstate<=4; end if; 17 when 2=> 18 if X='0' then Z<='0'; Nextstate<=4 19 else Z<='1'; Nextstate<=4; end if; 20 when 3=> 21 if X='0' then Z<='0'; Nextstate<=5 22 else Z<='1'; Nextstate<=5; end if; 23 when 4=> 24 if X='0' then Z<='1'; Nextstate<=5 25 else Z<='0'; Nextstate<=6; end if; 26 when 5=> 27 if X='0' then Z<='0'; Nextstate<=0 28 else Z<='1'; Nextstate<=0; end if; 29 when 6=> 30 Z<='1'; Nextstate<=0; 31 end case; 32 end process; 33 process (CLK) --State Register 34 begin 35 if CLK'event and CLK='1' then --rising edge of clock 36 State<=Nextstate; 37 end if; 38 end process; 39 end table; Submit your VHDL