(a) Write a behavioral Verilog description of the state machine that you designed in Problem 1.14. Assume that state changes occur on the falling edge of the clock pulse. Use a case statement together with if-then-else statements to represent the state table. Compile and simulate your code using the following test sequence:

X = 1011 0111 1000

X should change 1/4 clock period after the falling edge of the clock.

(b) Write a data flow Verilog description using the next-state and output equations to describe the state machine. Indicate on your simulation output at which times D and B should be read.
(c) Write a structural model of the state machine in Verilog that contains the interconnection of the gates and J-K flip-flops.

Data from Problem 1.14.

A sequential circuit has one input (X) and two outputs (D and B). X represents a 4-bit binary number N, which is input least significant bit first. D represents a 4-bit binary number equal to N – 2, which is output least significant bit first. At the time the fourth input occurs, B = 1 if N - 2 is negative; otherwise, B = 0. The circuit always resets after the fourth bit of X is received.