Write behavioral VHDL code that implements the state machine that you designed in the previous module. Use a case statement to represent the state table as illustrated in the code below. Use two processes one for the combinational logic and one for the state register. Add an asynchronous reset input.

1 entity SM17_2 is 2 port(X,CLK: in bit; 3 Z:out bit); 4 end SM17_2; 5 architecture Table of SM17_2 is 6 signal State, Nextstate: integer range 0 to 6:= 0; 7 begin 8 process(State,X) --Combinational Cicuit 9 begin 10 case State is 11 when 0=> 12 if X='0' then Z<='1'; Nextstate<=1; 13 else Z<='0'; Nextstate<=2; end if; 14 when 1=> 15 if X='0' then Z<='1'; Nextstate<=3 16 else Z<='0'; Nextstate<=4; end if; 17 when 2=> 18 if X='0' then Z<='0'; Nextstate<=4 19 else Z<='1'; Nextstate<=4; end if; 20 when 3=> 21 if X='0' then Z<='0'; Nextstate<=5 22 else Z<='1'; Nextstate<=5; end if; 23 when 4=> 24 if X='0' then Z<='1'; Nextstate<=5 25 else Z<='0'; Nextstate<=6; end if; 26 when 5=> 27 if X='0' then Z<='0'; Nextstate<=0 28 else Z<='1'; Nextstate<=0; end if; 29 when 6=> 30 Z<='1'; Nextstate<=0; 31 end case; 32 end process; 33 process (CLK) --State Register 34 begin 35 if CLK'event and CLK='1' then --rising edge of clock 36 State<=Nextstate; 37 end if; 38 end process; 39 end table;

This is the code for the state machine designed in the module before ( the code we have to work with)

entity adder8bit is port ( CLK, ClrN, Ad, Sh, SI: in std_logic ; Din: in std_logic_vector( 7 downto 0 ); SO: out std_logic; Dout: out std_logic_vector(7 downto 0)); end entity adder8bit;

architecture behavioral of adder8bit is signal test: std_logic_vector(7 downto 0 ):="00000000"; begin process (CLK, ClrN)

begin if (ClrN = '0')then test <="00000000"; elsif (CLK'event and CLK = '1' and Ad= '1') then test <= test + Din; elsif (CLK'event and CLK = '1' and Sh='1' and Ad='0') then test <= test(6 downto 0)&SI; elsif (CLK'event and CLK = '1' and Sh='0' and Ad= '0') then test <= test; end if; end process; Dout <= test; SO <= test(7); end behavioral; The directions for that code were the following

write a VHDL module for an 8-bit accumulator which can also shift the bits in the accumulators register to the left. If Ad = 1, the accumulator should add the value of the data inputs D to the value already in the accumulator. If Ad = 0 and Sh = 1, the bits in the accumulator should shift left (i.e., multiply by 2). If Ad = Sh = 0, the accumulator should hold its state. The accumulator should also have an active low asynchronous clear signal ClrN. Assume that carry-in and carry-out signals are unnecessary for this application. Use an overloaded"+" operator for addition. The test data we will be running through the module is the following, -reset -set Acc = 01100000 -set D = 11100010 -set Ad = 1 for 2 clock cycles = 0 for rest of the test -set Sh = 0 for 2 clock cycles = 1 for 2 clock cycles = 0 for the rest of the test.