1.2.4 A full adder has three inputs, a, b, cin (carry-in), and two output cout (carry-out), sum As the name implies the 2-bit output represents the result from computing binary addition of the three inputs. Based on this, complete the blanks marked with (ei11 in) in the VHDL code, provided below, to implement the full adder Company: METU-NCC Engineer: Your name goes here Create Date: 27/02/2012 Design Name: Full Adder Module Name: fulladd Logicfunc -Project Name: Lab 1 -- Target Devices: Cyclone III EP3C16F484C Description: Full adder VHDL design Dependencies: Revision: Revision 0.01 - File Created Additional Comments: Library IEEE use IEEE.STD LOGIC 1164.ALL use IEEE.STD LOGIC ARITH.ALL: use IEEE. STD LOGIC UNSIGNED.ALL entity fulladd is Port ( cin: in STD LOGIC (fin in) : in STD LOGIC; (fill in)in STD LOGIC (111 in) : out STD LOGIC (111 in)out STD LOGIC)