A full adder has three inputs, a, b, cin (carry-in), and two outputs, sum and cout (carry-out). As the name implies, the 2-bit output represents the result from computing binary addition of the three inputs. Based on this, complete the blanks marked with (fill in) in the Verilog code, provided below, to implement the full adder. Note that the main body of the code has been written three times using three different approaches for the high-level description of the full adder. Each of these approaches is important and becomes useful in addressing different problems. Complete the code segments for all three approaches. // Company: METU-NCC // Engineer: Your name goes here // Create Date: Date goes here // Design Name: Full Adder // Module Name : fulladd - Logicfunc // Project Name: Lab 1 // Target Devices: Cyclone III EP3C16F484C6 // Description: Full adder Verilog design // Dependencies: List code modules called by this module - none here. // Revision: // Revision 0.01 - File Created // Additional Comments: Information to make the code easier to follow. //Structural Approach// module fulladd (A, B, Cin, S, Cout); output (fill in); (fill in) A, B, Cin; (fill in) wl,w2,W3; xor G1 (fill in); (fill in) G2 (w1, A, B), G3 (w2, A, Cin), G4 (w3, B, Cin); (fill in) G5 (Cout, w1,w2,3); endmodule //Behavioral Approach, Continuous// module fulladd (fill in); output S, Cout; input A, B, Cin; wire (fill in); assign S= (fill in); (fill in) wl=A && B; (fill in) W2=A && Cin; (fill in) W3=B & & Cin; assign Cout= (fill in); endmodule 1/Behavioral Approach, Procedural// module fulladd (A, B, Cin, S, Cout); output S, Cout; input A, B, Cin; (fill in) S, Cout; always (fill in) if (Cin==0&A==0 & B==0) begin S=1'50; Cout= (fill in); end else if (Cin==0&A==0 & B==1) begin S=l'bl; Cout=l'bo; end else if (Cin==0 & A==1 & B==0) begin S= (fill in); Cout=1'b0; end else if (Cin==0 & A==1 & B==1) begin S=1'bo; Cout=l'bl; end else if (Cin==1 & A==0 & B==0) begin srl'bl; Cout=1'b0; end else if (Cin==1 & A==0 & B==1) begin S=1'bo; Cout= (fil1 in); end else if (Cin=-1 & A==1 & B==0) begin S=1'b0; Cout=1'bl; end else begin S= (fill in); Cout=1'bl; end endmodule A full adder has three inputs, a, b, cin (carry-in), and two outputs, sum and cout (carry-out). As the name implies, the 2-bit output represents the result from computing binary addition of the three inputs. Based on this, complete the blanks marked with (fill in) in the Verilog code, provided below, to implement the full adder. Note that the main body of the code has been written three times using three different approaches for the high-level description of the full adder. Each of these approaches is important and becomes useful in addressing different problems. Complete the code segments for all three approaches. // Company: METU-NCC // Engineer: Your name goes here // Create Date: Date goes here // Design Name: Full Adder // Module Name : fulladd - Logicfunc // Project Name: Lab 1 // Target Devices: Cyclone III EP3C16F484C6 // Description: Full adder Verilog design // Dependencies: List code modules called by this module - none here. // Revision: // Revision 0.01 - File Created // Additional Comments: Information to make the code easier to follow. //Structural Approach// module fulladd (A, B, Cin, S, Cout); output (fill in); (fill in) A, B, Cin; (fill in) wl,w2,W3; xor G1 (fill in); (fill in) G2 (w1, A, B), G3 (w2, A, Cin), G4 (w3, B, Cin); (fill in) G5 (Cout, w1,w2,3); endmodule //Behavioral Approach, Continuous// module fulladd (fill in); output S, Cout; input A, B, Cin; wire (fill in); assign S= (fill in); (fill in) wl=A && B; (fill in) W2=A && Cin; (fill in) W3=B & & Cin; assign Cout= (fill in); endmodule 1/Behavioral Approach, Procedural// module fulladd (A, B, Cin, S, Cout); output S, Cout; input A, B, Cin; (fill in) S, Cout; always (fill in) if (Cin==0&A==0 & B==0) begin S=1'50; Cout= (fill in); end else if (Cin==0&A==0 & B==1) begin S=l'bl; Cout=l'bo; end else if (Cin==0 & A==1 & B==0) begin S= (fill in); Cout=1'b0; end else if (Cin==0 & A==1 & B==1) begin S=1'bo; Cout=l'bl; end else if (Cin==1 & A==0 & B==0) begin srl'bl; Cout=1'b0; end else if (Cin==1 & A==0 & B==1) begin S=1'bo; Cout= (fil1 in); end else if (Cin=-1 & A==1 & B==0) begin S=1'b0; Cout=1'bl; end else begin S= (fill in); Cout=1'bl; end endmodule