$1.$ Create a $4-$Bit Ripple Carry Adder Module called "Adder$4"($Read the

:$-$ is $-$I

rea

ate

a new design source, and follow

accordingly for the $4-$Bit Ripple Carry Adder$)$:

a$.$ Define the Adder$4$ module with:

i$.$ A and B: $4-$bit input vectors for the numbers to be added.

ii$.$ cin: A $1-$bit carry$-$in input.

iii. sum: A $4-$bit output vector for the resulting sum.

iv$.$ Gout: A $1-$bit carry$-$out output for the overall addition result.

$($NOTE: A$,$ B and sum are defined as $4-$bit vectors rather than a single$-$bit value. This vector structure allows the adder to handle multiple bits simultaneously, effectively summing binary numbers with multiple bits. In contrast, cout remains a single$-$bit output, representing the carry$-$out signal that propagates to the next higher bit position in multi$-$bit arithmetic operations.

v$.$ carry: A $3-$bit internal wire array used to connect the carry$-$out of each Euldadder to the carry$-$in of the next.

b$.$ Instantiation of Full Adders

i$.$ Four EullAdder instances $($FA$0$ to FA$3)$ are used to add each bit of A and B$.$

ii$.$ Each Euldadder takes in a bit from A and B$,$ the carry from the previous adder, and outputs a sum bit and a carry$-$out bit.

iii. The carry$-$out of each adder is connected to the carry$-$in of the next stage, creating a ripple effect. Complete the two missing lines in the Adder $4$ module code as shown below. Use the completed code for your simulation.

module RippleCarryAdder$4($input $[3$:$0]$ A$,$ input $[3$:$0]$ B$,$ input cin, output $[3$:$0]$ sum, output cout$)$: wire $[2$:$0]$ carry; $//$ Internal wires to hold carry between full adders

$//$ Instantiate four EullAdder, modules

Eulladder FA$1(.$x$($AI$1]),.$y$($B$[1]),.$cin$($carry$[0]),.$sum$($sum$[1]),.$cout$($carry$[1]))$;

$($missing line$)$

$($missing line$)$

endmadule

$2.$ Designing testbench $\backslash (\backslash$sim $\backslash )$ de for the $4-$Bit Ripple Carry Adder $($Read the $-....$ Lto learn how to create a new testbench file, and follow accordingly for the $4-$Bit Ripple Carry Adder$)$:

a$.$ Define the Adder$4\_$tb module with:

i$.$ A and B: $4-$bit registers for the test input vectors, representing the numbers to be added.

ii$.$ cin: A $1-$bit register for the carry$-$in input.

iii. sum: A $4-$bit wire to observe the resulting sum.

iv$.$ cout: A $1-$bit wire to observe the carry$-$out output.

b$.$ Instantiation of Adder$4$:

i$.$ The dut $($Device Under Test$)$ is an instance of the RippleCarryAdder$4$ module.

ii$.$ Each I$/$O port in dut is connected to corresponding signals declared in the testbench.

c$.$ Test Cases:

i$.$ Each test case applies different values to A$,$ B$,$ and Gin, with a delay of $\backslash$#$100$ units between changes.

ii$.$ Comments next to each test case describe the expected result of the addition $($for example, $1+1=2).$

iii. After the last test case, $\backslash$$stop is used to end the simulation. Complete the two missing lines in the Adder$4$ module code as shown below. Use the completed code for your simulation.

$```$

timescale $1$ns $/1$ps

module RippleCarryAdder$4\_$th;

wire $[3$:$0]$ sum:

wire cout:

reg $[3$:$0]$ A$,$ B;

reg cin:

RippleCarryAdder$4$ dut$($A$($A$),.$B$($B$),.$cin$($cin$),.$sum$($sum$),.$sout$($cout$))$;

initial

begin

#$0$ A $=4\text{'}$b$0001$; B $=4\text{'}$b$0001$; cin $=0$;

#$100$ A $=4\text{'}$b$0011$; B $=4\text{'}$b$0101$; cin$=$ @;

#$100$ A $=4\text{'}$b$1111$; B $=4\text{'}$b$1111$; ciq $=1$;

#$100$ A $=4\text{'}$b$1010$; B $=4\text{'}$b$0101$; cin$=1$;

#$100$ A $=4\text{'}$b$1000$; B $=4\text{'}$b$0001$; cin$=0$:

$($missing line$)$

$($missing line$)$

#$100$ $stop:$//$ End simulation

end

endmadule

$```$

You are encouraged to experiment with different combinations to visualize the sums.

d$.$ Paste a screenshot of your simulation waveforms for all input combinations. If your input combinations are different from the provided testbench code, update the code above as required.