1.Study the following circuit and write a truth table to describe the behavior.

2. Write a Verilog module called mystery to implement the circuit above.

3.Write a test bench to fully test the mystery module created in step2.

4.Simulate the circuit using ISim and analyze the resulting waveform in comparison to the truth table from step 1

5.Take full screenshots of the source code of mystery module, the test bench Verilog file, and resulting simulation waveforms to be included in the lab report. Include your analysis of the resulting waveform to explain in detail how you can tell whether your Verilog implementation in Step 4 for the circuit is accurate