Adders: 1-bit Full Adder and 8-bit Full Adder

1. Draw the schematics of a 1-bit Full Adder and write a truth table for the inputs and outputs.
2. Write a Verilog module called fulladder to implement the full adder circuit.
3. Write a test bench for the Verilog module fulladder and make sure to include all the input combinations.
4. Simulate the circuit using ISim and analyze the resulting waveform.
5. Take full screenshots of all Verilog source codes and the resulting simulation waveform to be included in the lab report. Compare the simulation with the theoretical truth table derived in Step 3 and make any corrections in your Verilog design to ensure the correct implementation of the full adder. Include your comparison in the lab report.