$[20$ points$]$ Complete the following VHDL code for a module that is an N$-$bit serial$-$in$,$ serial$-$out left$-$shift register. Inputs to the shift register are bit signals: SI $($serial input$),$ Sh $($shift enable$),$ and CLK$.$ Your module should include a generate statement in the architecture. Use a DFF component instance inside the architecture of LeftShiftRegister.architecture DFFBehavior of DFF isbeginprocess $($Clk$)$beginif Clk'event and Clk $=\text{'}1\text{'}$ thenQ D;end if;end process;end DFFBehavior;entity LeftShiftRegister isgeneric$($N: integer:$=4)$;port$($SI$,$ Sh$,$ CLK: in bit;Q: inout bit$\_$vector$($N$-1$ downto $0)$;SO: out bit$)$;end LeftShiftRegister;architecture LSRBehavior of LeftShiftRegister isend LSRBehavior;