Consider the universal shift register with synchronous parallel load and falling edge triggered shown in the following figure: SI Reset Left/Right LIS Clock 8-bit Shift Register with Parallel Load R, Rs Rs R, R; R, R, R The register has 8-bit parallel inputs RO to R7 and a serial input bit SI and 8-bit outputs Q0 to Q7. When the control signal L is O the register is in parallel mode and it will load the parallel inputs RO to R7 at falling edge of the next clock cycle. When Lis 1 the register act as a shift register and it will load the serial input Sl. The shift direction is controlled by the signal Left_right, where it will shift to the left if Left_right is 1 and to the right otherwise. The roaictor has a Racot cinchronous cianal that will clear the nutnute at tha novt clack cuclo acer by Le MCGM STILL OG GLU LLC the right otherwise. Time left 1:00:10 The register has a Reset synchronous signal that will clear the outputs at the next clock cycle when Reset is 1. Complete the following VHDL code that provides the design of this register LIBRARY ieee; USE ieee.std_logic_1164.all: ENTITY shiftsync IS GENERIC (N: INTEGER :=8); PORT(Clock, SI, LEFT_RIGHT, Reset,L : IN STD_LOGIC; R: IN STD_LOGIC_VECTOR(N-1 DOWNTO 0); Q: BUFFER STD_LOGIC_VECTOR(N-1 DOWNTO 0)); END shiftsync; ARCHITECTURE Behavior of shiftsvnc IS BEGIN Time left 0:59:46 PROCESS BEGIN IF Reset='1' THEN ELSIF L = '0' THEN ELSIF THEN Q '0') --- - UNUM THEN ELSIF Q '0') Q Q; WAIT UNTIL Clock'EVENT AND Clock='1; Complete the behavioral VHDL code of an Arithmetic Logic Unit that has 4 inputs A. B. fand FN. A