$2.(25$ points$)$ Assume that individual stages of a processor's datapath has the following latencies $($no two stages can occur in parallel$)$: IF ID EX MEM WB $200$ps $300$ps $100$ps $250$ps $250$ps Also, assume that the relative frequency of instructions executed by this processor are broken down as follows: Conditional Branches Instruction Class ALU Relative Freqency $50\%$ Stages IF$,$ ID$,$ EX$,$ WB $10\%$ Load from Memory Store to Memory $25\%15\%$ IF$,$ ID$,$ EX$,$ MEM, WB IF$,$ ID$,$ EX$,$ MEM IF$,$ ID$,$ EX $($a$)(5$ points$)$ What is the clock rate of the processor assuming that it is implemented in a pipelined fashion? $($b$)(10$ points$)$ Assuming the pipelined implementation for the processor, calculate the global CPI for the processor. In this question, you can assume that there are no memory stalls or hazards. $($c$)(10$ points$)$ Assuming the non$-$pipelined implementation for the processor, calculate the global CPI