In this exercise,we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:

IF	ID	EX	MEM	WB
250 ps	350 ps	150 ps	300 ps	200 ps

Also, assume that instructions executed by the processor are broken down as follows:

ALU/Logic	Jump/Branch	LDUR	STUR
45%	20%	20%	15%

4.16.1 [5] <4.5> What is the clock cycle time in a pipelined and non-pipelined processor?

4.16.2 [10]<4.5>WhatisthetotallatencyofanLDURinstructioninapipelined and non-pipelined processor?

4.16.3 [10] <4.5> If we can split one stage of the pipelined datapath into two new stages, each with half the latency of the original stage, which stage would you split and what is the new clock cycle time of the processor?

4.16.4 [10]<4.5>Assumingtherearenostallsorhazards,whatistheutilization of the data memory?

4.16.5 [10]<4.5>Assumingtherearenostallsorhazards,whatistheutilization

of the write-register port of the Registers unit?