$2.(4$ pts$)$ In this exercise, we examine how pipelining affects the clock cycle time of the processor. Problems in this exercise assume that individual stages of the datapath have the following latencies:

IF ID EX MEM WB

IF ID EX MEM WB

$250$ps $300$ps $200$ps $300$ps $150$ps

a$.(2$ pts$)$ What is the clock cycle time in a pipelined and non$-$pipelined processor?

b$.(2$ pts$)$ What is the total latency of a ld instruction in a pipelined and non$-$pipelined processor?