2. [5] (Q.3-18) Suppose we have a deeply pipelined processor, for which we implement a branch-target buffer for the conditional branches only. Assume that the misprediction penalty is always four cycles and the buffer miss penalty is always six cycles. Assume a 75% hit rate, 80% accuracy, and 25% branch frequency. How much faster is the processor with the branch-target buffer versus a processor that has a fixed three-cycle branch penalty? Assume a base clock cycle per instruction (CPI) without branch stalls of one