Suppose we have a deeply pipelined processor, for which we implement a branch-target buffer for the conditional branches only. Assume that the misprediction penalty is always six cycles and the buffer miss penalty is always five cycles. Assume a 60% hit rate, 70% accuracy, and 30% branch frequency. How much faster is the processor with the branch-target buffer versus a processor that has a fixed four-cycle branch penalty? Assume a base clock cycle per instruction (CPI) without branch stalls of one.