8. Suppose we have a deeply pipelined processor, for which we implement a branch- target buffer for the conditional branches only. Assume that the misprediction penalty is always five cycles and the buffer miss penalty is always three cycles. Assume a 95% hit rate, 85% accuracy, and 25% branch frequency. How much faster is the processor with the branch-target buffer versus a processor that fixed three-eyel without branch stalls of one. has a e branch penalty? Assume a base clock cycle per instruction 7. Show the timing of problem 5 instruction sequence for the 5-stage with full forwarding and bypassing hardware. Assume that the predicting it as not taken. If all memory references take 1 cycle, how many cycles does this loop take to execute? RISC pipeline branch is handle d by