2. Assume that our MIPS processor has six 32 bit registers and eight memory locations. Each memory location holds 32 bits of data. The naming convention for the registers and the memory are shown in the table below.

Table 1:

Register values, Register Initial Value, I1, I2, I3, I4, I5, I6, I7

R1, 4, , , , , , ,

R2, 16, , , , , , ,

R3, 12, , , , , , ,

R4, 20, , , , , ,

R5, 12, , , , , , ,

R6, 14, , , , , , ,

Table 2:

Memory values, Address Initial Value, I1, I2, I3, I4, I5, I6, I7

0, 10, , , , , , ,

4, 10, , , , , , ,

8, 18, , , , , , ,

12, 30, , , , , ,

16, 50, , , , , ,

20, 24, , , , , , ,

24, 16, , , , , , ,

28, 0, , , , , , ,

a. Now, let us assume that an array A with 3 integer (word) elements is stored starting from memory address zero and another array B with 4 integer (word) elements is at stored starting from memory address 16. That is, address of A[0] is 0, while the address of B[0] is 16. With this information, fill the register value and memory tables for the following sequence of instructions. I1, I2, etc denote the instruction number while LABEL denotes the target for the branch, if taken.

I1 : lw R3, 4(R1)

I2 : lw R4, 0(R1)

I3 : beq R3, R4, Label

I4 : sw R5, 0(R2)

I5 : j Exit Label

I6 : sw R6, 0(R2) Exit

I7 : . . .

b. What is the equivalent C code for the five instructions from part (a).