$2-$ Consider a dual$-$core $($P$1$ and P$2)$ SMP system with fully$-$associative caches, write$-$back, and LRU replacement

policy. Each cache has four blocks $($i$.$e$.,$ lines$)$ labeled $0,1,2,$ and $3.$ The shared main memory consists of $8$

blocks labeled $0,1,2,$dots,$7.$ Assume the same clock drives the processors and the memory bus and the following:

Each transaction $($request$/$response$)$ completes in one cycle.

In case of simultaneous bus requests from both processors, the priority is given in a round$-$robin fashion, i$.$e$.,$

$P1,P2,P1$ and so on$...,$ i$.$e$.,$ if the bus was last acquired by P$1$ then P$2$ will be given the priority.

For the following two asynchronous sequence of memory$-$access events, where boldface $($and shaded$)$ numbers

are for writes and the remaining are for reads, trace the execution of these block accesses on the two processors

using the MESI coherence protocol.

P$1$: $0,0,0,1,1,4,3,3,5,5,5$

P$2$: $2,2,0,0,7,5,5,5,7,7,0$

Clearly indicate all the operations performed in each cycle in the "Comments" column; i$.$e$.,$ processor request

$($PrRd$-$hit$/$miss or PrWr$-$hit$/$miss$),$ bus request $($BusRd $($S or $S^{\text{'}}),$ BusRdX, BusUpgr$),$ and whether a cache

$($Flush$)$ or main memory $($MM responds$)$ responds to complete the transaction. The first bus transaction is shown

below, where memory block number is indicated in parenthesis.

T indicates the cycle. For P$1$ and P$2$ columns, $b_{?}$ indicates when a request $($read$/$write$)$ is first issued for block b$.0-3$ columns

indicate the state of the cache block $b($and memory block number indicated in parenthesis$).$ B column indicates which processor

has access to the bus and $h$ column indicates whether there was a cache hit.