2. Consider executing the following assembly code in MIPS five stage (IF, ID, EX, ME, WB) pipeline model: g. Assume at most two instructions (one ALU/branch and one load/store) can be issued at each cycle, data access from/to memory does not interfere the instruction fetch, data forwarding is implemented, branch result is available at the end of the ID stage, loops are unrolled four times with unnecessary loop overhead eliminated, and you may reorder the instructions to avoid the pipeline stalls. Complete the execution diagram for one unrolled-iteration (i.e., 4 original iterations). On average, how many cycles are needed to finish one original iteration if there are infinite numbers of iterations