2. Consider executing the following assembly code in MIPS five stage (IF, ID, EX, ME, WB) pipeline model: Assume at most two instructions (i.e., one ALU/branch and one load/store) can be issued at each cycle, data access from/to memory does not interfere the instruction fetch, data forwarding is implemented, branch prediction is perfect (i.e., branch does not stall), and you may reorder the code within one iteration to avoid the pipeline stalls. Complete the execution diagram for one iteration. On average, how many cycles are needed to finish one original iteration if there are infinite numbers of iterations