2. Consider the circuit shown below. 2ns ons CLK X 2ns R P ons 2ns The circuit has primary input CLK labeled on the left, and primary outputs X and Y shown on the right. The delays of each gate in the circuit are shown beside the gate. Assume that CLK switches from 0 +1 at time Ons, from 1 + 0 at time 25ns and from 0 +1 at time 50ns. (a) Why is it not possible to run Static Timing Analysis (STA) on this circuit? (b) Find the static values of all the nodes in the circuit (CLK, P, Q, R, X and Y) from time - to Ons. (c) Now run Event Driven Timing Simulation on the circuit, up to time 70ns. Show your event table (with entries for node name, time, as well as the values of the node before and after the time listed). Indicate the induced event(s) by means of arrows. (d) Now draw the waveforms of signals X and Y (e) Based on your answer to the previous part, what is the functionality of the above circuit? 2. Consider the circuit shown below. 2ns ons CLK X 2ns R P ons 2ns The circuit has primary input CLK labeled on the left, and primary outputs X and Y shown on the right. The delays of each gate in the circuit are shown beside the gate. Assume that CLK switches from 0 +1 at time Ons, from 1 + 0 at time 25ns and from 0 +1 at time 50ns. (a) Why is it not possible to run Static Timing Analysis (STA) on this circuit? (b) Find the static values of all the nodes in the circuit (CLK, P, Q, R, X and Y) from time - to Ons. (c) Now run Event Driven Timing Simulation on the circuit, up to time 70ns. Show your event table (with entries for node name, time, as well as the values of the node before and after the time listed). Indicate the induced event(s) by means of arrows. (d) Now draw the waveforms of signals X and Y (e) Based on your answer to the previous part, what is the functionality of the above circuit