2- Correct the code below and precise his function (5 points) library ieee; use ieee.std_logic_1164.all; entity circuit is port (e1,e2, e3, e4: in std_logic; s: in std_logic); end circuit; architecture archi circuit of circuit is signal s1, s2, s3 : std_logic; component fct port (a, b: in std_logic; S: out std_logic); end fct: begin cmp1 : fct port map (ac-e1, bcee2, sc=s1); cmp2: fet port map (ac-e3, bce4, Sc=s2); cmp3: fet port map (acmel, bc=e3, S