$2.$ Draw the logic block diagram for a memory with $8$ K words of data, where each word is $16$ bits. The memory accesses the data in chunks of one word $($i$.$e$.,$ for each read or write, one word of data is read out or written in$,$ respectively$).$ Show the optimum size for the memory array, the number of address and data lines required, and any supporting logic blocks $.$