2. Given the follow signal definitions: type typel is array (7 downto 0) of std_logic; type type2 is array(1 to 3) of typel; type type3 is array(1 to 2) of type2; type type4 is array(1 to 3, 7 downto 0) of std_logic; signal sl: bit; signal s2: bit_vector(0 to 4); signal s3: std_logic_vector (7 downto 0); signal s4: signed (5 downto 0); Sigral s5: typel; Signal s6: type3; signal s7: type4; State whether the following assignments are legal or not. If the assignment is illegal, explain the errors. (a)si := s2 (4); (b) s4