$2.($i$)$ Design a Modulo$-$N counter where N is variable. Depending on an external input S$1$S$0$ the counter counts as per table given below:

Following components are only available for your design:

$1.$ One $4-$bit binary up counter with active high synchronous load $($LD$)$: $($i$.$e$.,$ when the value at LD input is logic $1$ the counter loads the data at its parallel inputs $($I$3$I$2$I$1$I$0)$ to its outputs Q$3$Q$2$Q$1$Q$0$ upon receiving a clock pulse at its CLK input. If $\backslash ($ L D$=0\backslash )$ the counter acts as a $4-$bit binary up counter and does counting upon receiving each clock pulse$)$;

$2.4$:$1$ MUXs $-4$ Nos.;

$3.\backslash (2\backslash$mathrm$\{$i$\}/\backslash$mathrm$\{$p$\}\backslash )$ EXOR gates $-4$ Nos.;

$4.\backslash (4\backslash$mathrm$\{$i$\}/\backslash$mathrm$\{$p$\}\backslash )$ NOR gate $-1$ No$.$

$($Hint: Use EXOR gates for comparison of counter output with defined count sequence as per S$1$S$0)$

$($ii$)$ Implement the Boolean expression F $($W$,$ X$,$ Y$,$ Z$)\backslash (=\backslash$Sigma $\backslash$mathrm$\{$m$\}(0,2,5,7,10,11,14,15)\backslash )$ using one $\backslash (4$: $1\backslash )$ MUX and additional logic gates $($minimum number$).($Use $\backslash (\backslash$mathrm$\{$Y$\},\backslash$mathrm$\{$Z$\}\backslash )$ as selection lines for the MUX$)$ Assume inputs are available both in true and complement forms.