Question: 2. Modify the below VHDL code (four-bit up-counter) by adding a parameter that sets the number of flip-flops in the counter. LIBRARY ieee : USE

2. Modify the below VHDL code (four-bit up-counter) by adding a parameter that sets the number of flip-flops in the counter. LIBRARY ieee : USE iece std.logic. 1164.all: USE tece stdJogic_junsigned all ENTITY upcount IS PORT (Clock, Resetn. E : IN STD.LOGIC: Q : OUT STD.LOGIC VECTOR (3 DOWNTO 0)) END upcount: ARCHITECTURE Behavior of upcount IS SIGNAL Count : STD.LOGIC VECTOR (3 DOWNTO O): BEGIN PROCESS (Clock, Resetn) BEGIN IF Resetn = '0' THEN Count

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